1. Technical Field
The present disclosure relates to an electrostatic discharge protection circuit for an integrated circuit, and to an integrated circuit comprising such a protection circuit.
2. Description of the Related Art
An integrated circuit (IC) comprising sensitive internal circuitry may be subjected to an Electrostatic Discharge (ESD) event consisting of a very high voltage applied to pins or pads of the circuit. Such an event may damage the circuitry and occur during the manufacture, assembly, testing, or normal handling and operation of the integrated circuit or of a product in which the integrated circuit is incorporated. Clamp circuits or “shunts”, such as a large MOSFET transistor, are therefore commonly provided as part of an ESD protection circuit to couple power and ground supply rails of the IC in response to a detection of an ESD event. The high voltage received is thereby dissipated through the shunt and the sensitive circuitry is protected from damage.
FIG. 1 shows a conventional integrated circuit IC comprising an ESD protection circuit EC along the lines of the circuit disclosed by U.S. Pat. No. 5,946,177. The integrated circuit comprises a voltage pad PV coupled to a power supply rail PSR, a ground pad PG coupled to a ground supply rail GSR, and an input/output pad P0. The integrated circuit IC further comprises internal circuitry CT and an ESD protection circuit EC, both linked to the supply rails PSR, GSR.
The ESD protection circuit EC comprises an input 1, a trigger 2, a trigger output node N3, a delay 3, and a shunt transistor TN1 configured to couple the rails PSR, GSR of the integrated circuit IC. Input 1 comprises an input node N1 and diodes D1, D2. Input node N1 is coupled to the pad P0 and to the supply rails PSR, GSR via diodes D1, D2 respectively. As diodes D1, D2 are on the ESD discharge path, they are relatively large.
The trigger 2 comprises a resistor R1 and a capacitor C1 in series forming an RC transient filter, a detection node N2, and a PMOS transistor TP1. Resistor R1 has one terminal coupled to the power supply rail PSR and one terminal coupled to node N2. The capacitor C1 has one terminal coupled to node N2 and one terminal coupled to the ground supply rail GSR. Transistor TP1 has a gate terminal G driven by node N2, a source terminal S coupled to the power supply rail PSR, and a drain terminal D coupled to the trigger output node N3.
The delay 3 comprises a resistor R2 and a capacitor C2. Resistor R2 and capacitor C2 each have one terminal coupled to node N3 and one terminal coupled to the ground supply rail GSR. Capacitor C2 may be a gate-body parasitic capacitance of transistor TN1 or a physical capacitor. Finally, the shunt transistor TN1 has a control terminal (gate terminal G) driven by node N3, a drain terminal D coupled to the power supply rail PSR, and a source terminal S coupled to the ground rail GSR.
Circuit EC provides protection from positive ESD events applied between pad PV and a grounded pad PG, negative ESD events applied between pad PG and a grounded pad PV, as well as ESD events between pad P0 and either of pads PV, PG.
FIG. 2 shows voltages V with respect to time t at various points of the ESD protection circuit EC during an ESD event. Five voltages VP, VG, V1, V2, and V3 are shown in FIG. 2, each corresponding to the voltage at a respective part of the circuit of FIG. 1. Voltage VP is the voltage present on the power supply rail PSR, voltage VG is the voltage present on the ground supply rail GSR, and voltages V1, V2, V3 are the voltages present at nodes N1, N2, N3 respectively.
At a time t1, an ESD event occurs, for example by applying test probes between pad P0 and the ground pad PG. Voltage V1 present at the pad P0 increases rapidly. Voltage VP present on the power supply rail also increases, but to a peak voltage value much less than that of voltage V1 due to the voltage drop across diode D1 and due to parasitic resistances (not shown) present in the supply rails. Voltage VG on the ground supply rail increases slightly, but is maintained relatively low by ground pad PG, which is connected to ground.
Voltage V2 at node N2 is initially held low, at a voltage value less than that of the power supply rail. Consequently, transistor TP1 is in a conducting state. Node N3 is thus coupled to the power supply rail PSR, and voltage V3 increases towards voltage VP, setting the shunt transistor TN1 in a coupling state. The supply rails GSR, PSR are coupled, and the voltage VP on the power supply rail decreases.
Voltage V2 rises with a delay time set by the RC time constant determined by resistor R1 and capacitor C1. Eventually, voltage V2 passes the threshold voltage of transistor TP1, and transistor TP1 is set in a blocked state, isolating node N3. The delay 3 maintains transistor TN1 in a conductive state for the entire duration of the ESD event, which may be 500 nS or more. The voltage V3 at node N3 decreases with a value determined by resistor R2 and capacitor C2.
In normal operation of the integrated circuit IC, voltage V2 at node N2 is at a high voltage value, keeping transistor TP1 in a blocked state. A relatively constant voltage applied on the power supply rail PSR and its slight fluctuations are not detected by the trigger 2 and thus do not launch the operation of the protection circuit EC. Furthermore, resistor R2 keeps voltage V3 at node N3 at zero, such that the shunt transistor TN1 is maintained in a blocked state. Consequently, the ESD protection circuit EC does not interfere with the operation of the integrated circuit IC and the internal circuitry CT.